1.       5 years of hands on experience on high speed digital RTL design using verilog.

2.       Experience on developing simulation testbench.

3.       Experience on DC compiler synthesis tools.

4.       Expience on prime time static timing tools.

5.       Completed at least one million+ gate chip design projects from architectural phase to tape out. Video¡¢Audio decoder¡¢LCD controller experience is a plus.