1.       5 years of hands on experience on high speed digital RTL design using verilog.

2.       Experience on developing simulation testbench.

3.       Experience on synthesis tools.

4.       Experience on prime time static timing tools.

5.       Completed at least one million+ gate chip design projects from architectural phase to tape out.

6.       Knowledge on Video¡¢Audio¡¢H.264 design or telecommunication is preferred.